Raghunath Murali

Check out this video. It shows how graphene nanowires can be used as on-chip interconnects and at the same time also for cooling hot spots on-chip.

Graphene mobility on SiO2 is limited to 40,000 cm2/V-s by LA phonon scattering. Suspended graphene, on the other hand, has shown a mobility as high as 200,000 cm2/V-s - but suspended graphene is not directly usable for most electronic applications.  Usually only the best measurements (rather than averages) are reported in the literature for graphene mobility; an average graphene sample, using current techniques of flaking, could have mobilities far lower than the limit imposed by the SiO2 phonons - more like 5,000 to 10,000 cm2/V-s. This is because of impurity scattering that causes extra scattering events and increases the scattering rate.

A group from Penn State and Yale has reported graphene mobility on PZT substrates (Phys. Rev. Letters, April 3). The substrate-limited mobility is 70,000 cm2/V-s at room temperature.  So, if high-quality PZT substrates are easy to make, and if grown graphene layers can be transferred onto PZT substrates, we can expect a 2X improvement in the mobility limit imposed by the substrate.

A while back, DARPA created a program called CERA (Carbon electronics for RF applications) and funded two groups - one led by IBM and the other HRL. The aim is to use graphene for RF applications, and to grow graphene on large area substrates for use in integrated RF circuits. Now we are beginning to see initial results from research efforts.

In IEDM 2008, IBM reported the fabrication of RF transistors using flaked graphene. Around the same time, HRL too reported RF transistors - but using graphene grown on SiC. Ofcourse the HRL group’s fT was much lower than that of IBM since grown graphene is not yet as pristine as cleaved graphene. In their latest paper in Electron Device Letters (May), the HRL group reports results of RF transistors  on 2″ 6H-SiC substrates. The fT is reported to be around 5 GHz.

An interesting article by Begtrup et al (Nano Letters, May) reports a simple electromechanical memory device in which an iron nanoparticle shuttle is controllably positioned within a hollow nanotube channel. The shuttle memory has application for archival storage, with information density as high as 1e12 bits/in.sq, and thermodynamic stability in excess of one billion years. Pyrolysis of ferrocene in Argon at 1000 C was used to make nanotubes with the Fe particle.

Lithography has been a cornerstone for continued scaling of electronics, all the way from micron-sized transistors in the ’80s to 45 nm transistors in the current technology. Lithography for manufacturing has been primarily using optical techniques (rather than other types like electron beam, x-ray, ion-beam) where light of a certain wavelength is used to project an image on a wafer using a photomask inbetween the light source and the wafer. Current lithography in chip manufacturing uses a 193 nm wavelength source, and feature sizes as small as 40 nm are possible by using a combination of advanced techniques such as phase shift masking, double patterning, and wet lithography. Though the resolutions achieved are impressive, mask costs have risen due to the complexity. In addition, getting feature sizes below 30 nm will be an uphill task using 193 nm sources.  Thus there is a push toward EUV lithography which uses 13.6 nm sources.  At this small a wavelength, a quartz lens will absorb light than diffract it - thus all lenses for EUV are reflective, thereby increasing the cost and complexity through the roof.

Three papers on the recent issue of Science (May 15) detail various approaches to achieve sub-wavelength features using simpler techniques. Though the transition of these techniques to manufacturing is too early to predict, there is hope that these techniques will atleast enable cheaper and faster low-volume fabrication like that needed in R&D.

Dr. Perry from Georgia Tech writes…”The main concept behind the “subdiffraction” resolution approaches reported in this issue is the use of dual exposures to create a spatial exposure pattern. These beams can have a donutlike pattern—the beam that activates the patterning chemistry is surrounded by a ring of intensity of another beam that suppresses the activation while maintaining a valley (or node) at the center of the activating beam. The product of the activation peak and “deactivation” donut pattern gives a spatial dosing pattern that is substantially finer than the far-field diffraction pattern of a tightly focused optical beam.”

Two-Color Single-Photon Photoinitiation and Photoinhibition for Subdiffraction Photolithography
Timothy F. Scott, Benjamin A. Kowalski, Amy C. Sullivan, Christopher N. Bowman, and Robert R. McLeod (15 May 2009)     Science 324 (5929), 913. [DOI: 10.1126/science.1167610]

Confining Light to Deep Subwavelength Dimensions to Enable Optical Nanopatterning
Trisha L. Andrew, Hsin-Yu Tsai, and Rajesh Menon (15 May 2009)     Science 324 (5929), 917. [DOI: 10.1126/science.1167704]

Achieving {lambda}/20 Resolution by One-Color Initiation and Deactivation of Polymerization
Linjie Li, Rafael R. Gattass, Erez Gershgoren, Hana Hwang, and John T. Fourkas (15 May 2009)     Science 324 (5929), 910. [DOI: 10.1126/science.1168996]

One reason for the recent Silicon revolution is the advent of complementary metal oxide semiconductor (CMOS) technology; CMOS utilizes n-type and p-type transistors such that there is effectively no power drain from the power supply once a switching event has been executed.  In the absence of a CMOS type of structure, for example in NMOS technology that utilizes only n-type transistors, there is a constant power drain from the supply even when the device has finished switching its state. Thus, to obtain a traditional CMOS configuration, it is important to have both n-type and p-type transistors.

It is not clear if CMOS-type architectures would be used for post-Silicon technology but most graphene transistors fabricated to date exhibit p-type doping. A recent paper by the Dai group (Science, 8 May) discusses the fabrication of n-type graphene transistors by subjecting them to anneal in an ammonia environment. The results are promising in terms of maintaining a good on-off ratio with the doping.

Two reports in the recent issue of Nature (one from Hongjie Dai at Stanford, and the other from Jim Tour at Rice) report methods to “unzip” carbon nanotubes to make graphene sheets. While the Dai method has a better control over feature size, the Tour group is more scalable to mass production.

Freitag et al argue in their recent paper that umklapp scattering sets in at T>350K in graphene, thereby reducing the thermal conductivity from 5000 W/m-K to 850 W/m-K at T=800K. This measurement was made on a micron-wide (and long) graphene flake using spatially resolved Raman. The peak temperature in the graphene ribbon was found to be 1050K while the peak energy dissipation was found to be 210 kW/cm2.

Reference: Marcus Freitag*, Mathias Steiner, Yves Martin, Vasili Perebeinos, Zhihong Chen, James C. Tsang and Phaedon Avouris, “Energy Dissipation in Graphene Field-Effect Transistors,” Nano Letters, Advance Publication, 30 March 2009.

An interesting paper published recently talks about the experimental demonstration of a (primitive) logic gate.

Reference: Roman Sordan, Floriano Traversi, and Valeria Russo, “Logic gates with a single graphene transistor,” Appl. Phys. Lett. 94, 073305 (2009) (3 pages)

Check out the program here:
215th ECS Meeting at SF

Many interesting papers on graphene growth on SiC; one paper talks about initial results on 3C-SiC growth on (111) Si.