Two reports in the recent issue of Nature (one from Hongjie Dai at Stanford, and the other from Jim Tour at Rice) report methods to “unzip” carbon nanotubes to make graphene sheets. While the Dai method has a better control over feature size, the Tour group is more scalable to mass production.

Freitag et al argue in their recent paper that umklapp scattering sets in at T>350K in graphene, thereby reducing the thermal conductivity from 5000 W/m-K to 850 W/m-K at T=800K. This measurement was made on a micron-wide (and long) graphene flake using spatially resolved Raman. The peak temperature in the graphene ribbon was found to be 1050K while the peak energy dissipation was found to be 210 kW/cm2.

Reference: Marcus Freitag*, Mathias Steiner, Yves Martin, Vasili Perebeinos, Zhihong Chen, James C. Tsang and Phaedon Avouris, “Energy Dissipation in Graphene Field-Effect Transistors,” Nano Letters, Advance Publication, 30 March 2009.

An interesting paper published recently talks about the experimental demonstration of a (primitive) logic gate.

Reference: Roman Sordan, Floriano Traversi, and Valeria Russo, “Logic gates with a single graphene transistor,” Appl. Phys. Lett. 94, 073305 (2009) (3 pages)

Check out the program here:
215th ECS Meeting at SF

Many interesting papers on graphene growth on SiC; one paper talks about initial results on 3C-SiC growth on (111) Si.

A recent literature survey revealed that various types of graphene growth are giving promising sheet resistances. I like to think in terms of resistivity (u-ohm-cm) just for easy comparison to other well-known materials. So here is a quick comparison:

1. CVD Graphene - 30 u-ohm-cm
2. Graphene by reducing graphene oxide- 15,000 u-ohm-cm
3. Graphene on SiC- 5 u-oum-cm
4. Flaked graphene- 5 u-ohm-cm

Options 1 and 3 look quite impressive for electrical conduction. But what is rarely discussed is the possible resistivity when the material is patterned into a 1D conductor (like a nanowire). It is quite possible that even with perfect patterning, the nature of the material/substrate system may cause a decrease in conductivity when the material is converted from a 2D system to a 1D system. When imperfect edges are added (expected for current manufacturing technology), this problem becomes even more severe…

I decided to shift my blog from blogger to my own word-press powered site…

This week marked the first Graphene MRSEC workshop at Georgia Tech. With over 25 presentations and as many posters by various researchers around the US working mostly on epitaxial graphene. Exciting new results were presented on recent advances in achieving high-quality graphene on SiC as well as some chemical approaches to pattern/produce graphene. Check out the MRSEC link to the right for a list of the MRSEC PIs and their research areas.