One reason for the recent Silicon revolution is the advent of complementary metal oxide semiconductor (CMOS) technology; CMOS utilizes n-type and p-type transistors such that there is effectively no power drain from the power supply once a switching event has been executed. In the absence of a CMOS type of structure, for example in NMOS technology that utilizes only n-type transistors, there is a constant power drain from the supply even when the device has finished switching its state. Thus, to obtain a traditional CMOS configuration, it is important to have both n-type and p-type transistors.
It is not clear if CMOS-type architectures would be used for post-Silicon technology but most graphene transistors fabricated to date exhibit p-type doping. A recent paper by the Dai group (Science, 8 May) discusses the fabrication of n-type graphene transistors by subjecting them to anneal in an ammonia environment. The results are promising in terms of maintaining a good on-off ratio with the doping.