Raghunath Murali

By Kevin Brenner

Over the past few years, electrical interconnects have begun to play a more significant role in the limitations of chip performance. As transistors and minimum feature sizes are continually scaled down to improve performance and satisfy Moore’s Law, the current interconnect material, Cu, begins to rapidly degrade in performance. This degradation is an intrinsic material characteristic of Cu, and as a result of this new materials are needed to replace it for local interconnects as the line widths approach 20 nm.

One of the most promising materials to replace Cu is graphene, a monolayer of honeycomb-arranged carbon atoms. Graphene shares many of the desirable traits of Carbon Nanotubes, such as mechanical strength, ballistic transport and high mobility, but its epitaxial nature makes it desirable for standard photolithography techniques and integration into current CMOS processing. Although a process for the growth of large area graphene layers onto processable wafers is essential for graphene to force its way into mainstream technology, many of the electrical, thermal, and even optical properties of the material can be studied relatively easily through mechanical exfoliation. This technique entails using a scotch tape to peel off layers of flaked graphene from a bulk graphite source and deposit them onto a substrate for processing and testing. This flaked graphene provides a quick and easy method to fabricate graphene nanoribons (GNRs), i.e. graphene channels, for use in characterizing the limitations of the material and its potential to out perform Cu and other competitors for local interconnects. Although there is theoretical work to support graphene’s superior performance at narrow line widths, concrete experimental data is still needed to retain interest in the material and push research forward. Current work includes characterizing mobility at sub 30nm linewidths, current carrying capacity of GNRs, and means of chemically doping the material to lower resistivity