Raghunath Murali

By Yinxiao Yang

The arrival of the Information Age has been enabled and driven by the scalability of a silicon transistor and the computational strength of its CMOS-based architecture. As scaling – reduction of device dimensions to fit more transistors in a given area – in silicon soon reaches its practical limits, the pursuit for a material of choice in a post-CMOS world has begun. Akin to the switch from bipolar to MOSFET technology and from NMOS to CMOS architecture, the semiconductor industry is once again looking for a disruptive technology that further enables the scaling trends predicted by Gordon Moore.

Half a decade after its experimental discovery, graphene has quickly risen to eminence in the semiconductor industry’s search for a material superior to silicon electrically and from a systems perspective. Carbon nanotubes (CNT), for instance, have superior mobility to silicon; however, they are dogged at the manufacturing level by low device densities and poor controllability. Composed of a 2-D sheet of sp2 bonded carbon atoms, graphene has long been predicted to have remarkable electrical and mechanical properties, not to mention the novel physics unique to a (never before observed, stable) 2-D material.

The initial gold rush migration by researchers confirmed its extraordinary electronic properties – charge carriers behaving as Dirac fermions [1] and demonstration of the Quantum Hall effect at room temperature [2], both which indicate ultra-high mobilities. In the context of electronics, superior room temperature mobility suggests ballistic transport, which occurs when dimensions of the device are smaller than the carrier mean free path. In addition, the Dirac nature of its carriers indicate light-like behavior only with a velocity 300 times less than the speed of light. Combining both properties, ballistic and light-like carrier behavior, we could preferably engineer a device with ultra-fast operation and yet low power consumption. Imagine for a moment that carriers could zip across a graphene channel at a constant velocity, independent of the externally applied electric fields along the direction of propagation. Such a device consumes virtually zero power (ballistic transport) and requires ultra low biasing voltages.

The largest mobility achieved to date – 200,000 cm2/V•s in suspended graphene [3] – is very encouraging but what is equally attractive about graphene is manufacturability owing to its 2-D nature. Moreover the material’s large current carrying capacity encourages its application in chip interconnects, enabling the idea of a monolithic chip of graphene devices and interconnects. At the moment, material synthesis remains a major obstacle: high quality graphene, in which the highest mobility demonstrations have been achieved, is synthesized by mechanical cleaving, which like nanotubes lacks the density and control required for mass production. Growth methods – on SiC [4] and nickel [5] – provide a 2-D sheet of (few-layer) graphene but their lesser quality puts into question whether the advantages provided by graphene still offset the holistic advantages provided by silicon. Researchers are looking at both sides: the physics at the device level and a host of issues from fabrication to architecture at the systems level. Whether a graphene-based system emerges as a post-CMOS technology remains to be seen but it undoubtedly hinders upon the synergy of these efforts.

References:
[1] Novoselov, K. S., et al. Nature 438, 197–200 (2005).
[2] Zhang, Y., et al. Nature 438, 201–204 (2005).
[3] Bolotin, K. I. et al., Solid State Commun. 146, 351-355 (2008).
[4] Berger, C. et al. Science, 312, no. 5777, pp. 1191–1196 (2006).
[5] Reina, A. et al. Nano Lett. 9, 30–35 (2009).